Cadence has introduced one of the industry’s first proven IP packedollar series, allowing chip developers to implement and test PCIe 6.0 support, just weeks after PCI SIG published the final draft of the PCIe 6.0 standard. The company’s solution is now ready and will be used by those who want to add PCI Express 6.0 support to their systems in 2022-2023.

Sanjive Agarwala, corporate vice president and general manager, IP Group at Cadence, said in a statement, “We look forward to seeing positive results with TSMC and Cadence technologies as early adopters begin to explore the new PCIe 6.0 standard. ” said.

The company’s IP consists of a controller and a DSP-based PHY (physical interface). The controller features a multi-packet processing architecture that supports up to 1024-bit wide bus in x16 configuration, data transfer rate up to 64 GT/s (in both directions), and supports all the core features of PCIe 6.0.

This solution is designed for TSMC’s N5 (5nm) fabrication technology and can be used by developers of a variety of AI/ML/HPC accelerators, GPUs, SSD controllers, and other bandwidth-hungry ASICs that need to add PCIe 6.0 support as soon as possible. . Alongside the IP suite, Cadence also offers a test chip implemented using N5 that aims to test signal integrity at all data rates and performance of PCIe 6.0 applications.

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Michael Lewis


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