PCI-SIG has released the latest specification update of the PCIe Gen6 standard, an update that increases the interface’s data transfer rate to 64 GT/s per lane. PCIe 6.0 technology will use quad-level (PAM-4) signaling technology to achieve high speeds, increase reliability and maintain efficiency.
We expect the new standard to be used initially in areas such as high-performance computing and data centers. The differences between PCIe 6.0 and PCIe 5.0 are significant. A total of 256GB/s bandwidth is offered in 16 lanes in both directions. That aside, PAM-4 signaling technology, which was previously used mainly for high-end networking technologies, is also used. Forward Error Correction (FEC), Cyclic Redundancy Check (CRC), and Flit (flow control unit) based coding technologies for L0p power states will be used with PAM-4.
Maintaining signal integrity and efficiency at 64 GT/s with PAM-4 is quite difficult. As PCIe is an interface for internal connectivity, low latency is important as well as high speeds. To this end, PCIe 6.0’s FEC method, further enhanced with CRC, is tasked with providing low latency and eliminating the inevitable bit errors that occur at such high speeds when using PAM-4.
Note that hosts that support PCIe 6.0 will still provide backward compatibility. However, there is a bad point. The release of PAM-4 (and everything it requires) will inevitably increase the cost of PCIe 6.0 implementation, making PCIe 6.0 controllers and other physical layers need more power. On the other hand, it is said that with the new technology, better power efficiency will be offered compared to PCIe 5.0.
There are companies that are already developing chips with PCIe Gen6 support. Server and client platforms for 2022 only support PCIe Gen 5. In this context, we can expect PCIe Gen 6 devices to be released in 2023 or 2024.
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