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Just as DDR5 RAMs are starting to hit the market, JEDEC has released an update that adds a host of features designed to improve the efficiency, performance, and reliability of DRAM ICs. The JESD79-5A update also expands the capabilities of DDR5-5600 and DDR5-6400 memory modules.

The original JESD79-5 standard defines how DDR5 SDRAM works and includes a variety of features to enable long-term performance scaling, along with improved efficiencies and reliability of memory chips that operate at high frequencies and support high data transfer rates. The revamped specification set offers several complementary features designed to further improve efficiency, performance and reliability.

Added features include limited bug fix support, Soft Post-Package Repair (sPPR), Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension.

It is very difficult to produce DRAMs that operate at high frequencies and support high data transfer rates. However, it is even more difficult to produce efficient, fast and high-capacity chips using leading manufacturing technologies. Therefore, DRAM manufacturers will use some of their own tick testing and repair features. These new features will also reduce the cost of high-end DRAMs to some extent.

Since the DDR5 standard will continue to be in our lives for many years to come, it makes a lot of sense to add new features and improve the standard. In the meantime, as is usually the case, we’ll see how quickly DRAM manufacturers will incorporate new features into their products.

Along with new features, the JESD79-5A expands the timing definition and transfer rate of DDR5 up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings. This development will help the industry build an ecosystem for upcoming DDR5-5600 platforms.

AMD, Intel, Micron, Montage, Samsung and SK Hynix are the first to confirm the DDR5 additions introduced by the JESD79-5A update.


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Michael Lewis

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