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AMD announced the EPYC Milan-X processors with 3D stacked L3 cache, called 3D V-Cache, during its Accelerated Data Center event on Monday, November 8th. The red team incorporated 3D V-Cache technology into their existing EPYC Milan models with Zen 3 to build the new Milan-X chips and managed to add excess cache.

Thanks to the new technology, a total of 768 MB of L3 cache can be used per chip. This means that soon there will be dual socketollarsi servers with 1.5GB L3 cache in the system. AMD also shared a few examples of workloads that would benefit, and an impressive benchmark result that showed a 60% performance increase. The chips, codenamed Milan-X, will be available in the second quarter of 2022, but are currently available as a preview sample on Azure.

The Reds first unveiled its 3D V-Cache technology at CES 2021 and showed off a third-generation Ryzen prototype equipped with an additional L3 cache unit. 3D V-Cache uses a new hybrid-binding technique that combines an additional 64MB of 7nm SRAM cache stacked vertically on top of Ryzen computing chips to triple the amount of L3 cache.

AMD claimed that it provides a performance increase of up to 15% in some games. In other words, these processors may even make a name for themselves in the field of gaming when they are released early next year.

The 3D V-Cache technology has been talked about for a long time and there is a possibility that this technique can be used in Infinity Cache caches in Zen cores and even Radeon cards. Now AMD is bringing this technology to their long-rumored Milan-X data center processors, but they haven’t shared full details of the new chips yet. In addition, it has been confirmed that the chips will come in at least 16, 32 and 64 core variants.

As with its consumer derivatives, AMD places a single 6x6mm L3 cache layer directly on top of the L3 cache already present in every CCD (computing chip). Each CCD had 32 MB of L3 cache before the change. The vertically stacked L3 cache unit adds another 64 MB cache, bringing the cache per CCD to a total of 96 MB. Milan-X chips will extend to 64-core models with eight CCDs, meaning a total of 768MB of L3 cache per chip will be offered.

Vertically stacked L3 cache increases overall latency by roughly 10%. On the other hand, AMD continues to use the same Zen 3 cores as normal. The control circuit for 3D V-Cache was added as a forward-looking design choice during the initial design phases. That is, existing EPYC Milan chips are adopted as the building block, so the chips use SP3 slots on EPYC servers and a BIOS update is required.

AMD underlined that the solderless hybrid bonding technique, which enables 3D V-Cache technology, has many benefits such as 200 times increase in interconnection density compared to 2D chips, 15 times increase in density compared to micro-bump 3D packagedollarseme, and 3 times energy efficiency gain. The company also says that hybrid coupling also improves thermal values, transistor density and interconnect pitch over other 3D approaches, making it the most flexible active-on-active silicon stacking technology.

Additionally, the red team said that although it has worked with several partners to create a series of certified software packages, no software changes are required to take advantage of the increased cache capacity.

As for performance, Milan-X has been claimed to deliver an increase of up to 50% in certain ‘targeted workloads’ consisting largely of a variety of product development software. AMD touted the performance of existing AMD EPYC Milan models across three workloads, showing that the two EPYC 75F3s beat the two Intel Xeon 8362s in three of those workloads.

The official features or price speculation of the new EPYC processors have not been announced yet. However, you can see the technical specifications based on historical information in the table below and this table will be updated after the official announcement.

Azure HBv3 Virtual Machines with Milan-X CPUs

Microsoft has released the following performance results for Milan-X HBv3 VMs:

  • Up to 80% higher performance for CFD workloads.
  • Up to 60% higher performance for EDA RDollars simulation workloads.
  • Up to 50% higher performance for open finite element analysis workloads.
  • Up to 120 AMD EPYC 7V73X CPU cores (EPYC with 3D V cache, “Milan-X”)
  • Up to 96MB of L3 cache per core (3x higher than standard Milan CPUs and 6x higher than “Roman” CPUs)
  • 448GB of RAM
  • 2 x 900GB NVMe SSD (3.5GB/s (read) and 1.5GB/s (write), big block IO)

Expected AMD EPYC Milan-X Processor Specifications

CPU Core/
Thread
Base Clock Boost Clock TDP L3 Cache (L3 + 3D V-Cache)
EPYC 7773X 64/128 2. 2GHz 3. 5GHz 280W 768 MB
EPYC 7573X 32/64 2. 8GHz 3. 6GHz 280W 768 MB
EPYC 7473X 24/48 2. 8GHz 3. 7GHz 240W 768 MB
EPYC 7373X 16/32 3. 05GHz 3. 8GHz 240W 768 MB

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Michael Lewis

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