AMD brought a breath of fresh air to the chip world with its presentation at Computex 2021. The company made a striking statement, announcing its 3D stacked chip design based on Zen 3, which will go into production this year. These new chips have an additional 64MB of 7nm SRAM cache (called 3D V-Cache) stacked vertically on top of the core complex (CCD) to triple the amount of L3 cache for CPU cores. This technique can provide an incredible L3 cache of up to 192MB per Ryzen chip, which is a huge improvement over the current 64MB limit.
AMD CEO Lisa Su showed an already working prototype Ryzen 9 5900X chip and a pretty impressive gaming demo thanks to the new architecture: The gains in 1080p gaming average around 15%. In normal conditions, this much gain can be achieved with a new processor microarchitecture and/or compute node. So either engineers need to sit down and improve the processor design or move to a lower nm. However, AMD achieved this success with the 7 nm node and Zen 3 architecture used in standard Ryzen 5000 models.
AMD connects the 3D cache to the top of the Ryzen CCD with TSVs (connection through silicon) providing up to 2TB/s of bandwidth between the chip and cache. This technique is made possible by TSMC’s 3DFabric technology, which we discussed here before. AMD demonstrated the new design through an animation:
When you add the cache chip on top of the chip, it creates a bulge. This of course poses a problem. Here, AMD refines the 3D cache die and adds structural silicon to the chip, making the chip a regular Ryzen processor.
Lisa Su showed off a prototype Ryzen 9 5900X with 3D chiplet technology fresh out of production. You can see the 6 x 6mm hybrid SRAM attached to the top of the chiplet (left chip in the image above). Finished processors will have 96MB of cache per CCD, which is an incredible number of almost 192MB of L3 cache for 12 or 16 core Ryzen 5000 processors.
AMD has used a hybrid connectivity approach that offers 200 times the density of 2D chipledollarserine interconnects in TSVs. This means a 15-fold improvement in interconnection density and a 3-fold improvement in interconnection energy efficiency compared to 3D applications with microprotrusions.
Su said these advances have been achieved thanks to a chip-to-chip interface that uses a micro-overhang, direct copper-copper bond to improve thermals, density and interconnection range, in addition to delivering incredible energy savings. The combination of these features makes the approach the most advanced and flexible active-active silicon stacking technology in the world, Su said.
Su compared the Ryzen 9 5900X prototype, which uses the new 3D V-Cache, to a standard 5900X, where both chips are fixed at a clock speed of 4.0 GHz. The 3D prototype saw a 12% increase in Gears 5.
Su also showed a broader comparison chart showing that the Ryzen 9 5900X with 3D V-Cache technology provides an average of 15% more performance at 1080p to achieve its goal. According to this table, the processor with 3D V-Cache provides higher performance in all games such as Dota 2, Monster Hunter World, League of Legends and Fortnite.
AMD told Tom’s Hardware that Zen 3 Ryzen processors with 3D V-Cache will go into production this year. The technology currently consists of a single layer of L3 cache, but the underlying technology supports stacking of multiple dies. The technology also does not require any special software optimizations and does not impose any significant overhead in terms of latency and thermals.
However, this is the first use of stacking technology – AMD may use it for other functions in the future. The implications of this for both the customer and the corporate side will be profound, so we’ll be on the lookout for more details.